DSP编译器的体系结构驱动计算排序和代码生成方法

Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems Pub Date : 1994-12-05 DOI:10.1109/APCCAS.1994.514541

J. Vilasdechanon, K. Likit-Anurucks, N. Sugino, A. Nishihara

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引用次数: 0

摘要

提出了一种考虑目标DSP体系结构(累加器数目、总线结构和多操作指令码)的DSP编译器计算排序和代码生成方法。将计算排序和代码生成合并为一步，可以得到较好的DSP编译结果代码。虽然本工作仅使用/spl mu/PD 7720作为目标DSP，但该方法可以应用于其他DSP。

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Architecture driven computational ordering and code generation method for DSP compiler

A computational ordering and code generation method for DSP compiler, which take the target DSP architecture, i.e., the number of accumulators, bus structure and multi-operation instruction code, into consideration is proposed. By combining computation ordering and code generation into one step, a better outcome code of DSP compiler may be obtained. Although only /spl mu/PD 7720 is used as target DSP in this work, the method may be applied to other DSPs.

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Proceedings of APCCAS'94 - 1994 Asia Pacific Conference on Circuits and Systems

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