Equalizer-Free Clock Recovery for PAM-4 Optical Interconnects

One of the critical operations in high-speed serial link receiver design is the recovery of clock embedded in the received data signal. If the received signal eye is not open, clock recovery becomes challenging. We present full-rate and halfrate clock recovery architectures for unequalized input signals with PAM-4 modulation. The proposed architectures comprise independent frequency and phase recovery loops for locking the voltage controlled oscillator frequency and phase to those of the incoming signal. This architecture is validated using simulations in Verilog-A for 100 Gbps PAM-4 signals extracted for optical fiber links of different fiber lengths. This system can recover the clock for the data obtained from a lkm standard single-mode fiber link, which otherwise gives a completely closed eye at the receiver input.