基于改进并行混合符号数(MPHSD)技术的最优加法算法的开发

V. Awasthi, K. Raj
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摘要

有符号数字(SD)数字系统提供了恒定时间加法的可能性,消除了数字间进位传播。本文用异步加法器对两类并行加法器的时延、面积和功率特性进行了研究。随着高速处理器的发展,总是需要在面积和执行时间之间进行权衡,以产生具有低功耗的最合适的实现。本文提出了一种采用有符号和混合有符号数算法的最优高速快速加法器算法。与传统的纹波进位加法器和进位前移加法器相比,这种改进的并行混合符号数加法器具有速度快、面积小的优点。由于冗余逻辑,MPHSD加法器需要更多的配置逻辑块(CLB)来优化执行时间、面积和功率。通过对其成本和性能进行详细分析,还可以评估其相对优点和缺点。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Development of optimum addition algorithm using modified parallel hybrid signed digit (MPHSD) technique
Signed digit (SD) number systems provide the possibility of constant-time addition, where interdigit carry propagation is eliminated. In this paper, two classes of parallel adder are surveyed with an asynchronous adder based on their delay, area and power characteristics. With the development of high speed processors, a tradeoff is always required between area and execution time to yield the most suitable implementation with low power consumption. In this paper, we proposed an optimum high speed fast adder algorithm by using signed and hybrid signed digit algorithms. This modified parallel hybrid signed digit (MPHSD) adder has high speed and less area as compare to conventional adders like ripple carry adder and carry lookahead adder. The MPHSD adder require few more configuration logic blocks (CLB's) because of redundant logic to optimize execution time with area and power. A relative merits and demerits is also evaluated by performing a detailed analysis in terms of its cost and performance.
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