Development of Automation System for HDL Modeling of the Communication Subsystem for Networks-on-Chip

With the active development and application of multi-core systems-on-chip, the design of efficient communication systems- on-chip is becoming a particularly challenging task. Designing a communication subsystem of networks-on-chip (NoCs) is a time-consuming process whose task is to select the optimal characteristics in a given range of values. Low-level modeling is an integral design step that allows obtaining accurate network characteristics, although it is time-consuming compared to high-level modeling. Most low-level NoC models include all the system-on--chip (SoC) components, thus slowing down modeling the communication subsystem (because to check one parameter, it is required to simulate the entire system). The proposed low-level model of a communication subsystem allows for automated generation of HDL model, as well as for modeling of both topology and routing algorithms for NoCs. The experiments carried out as exemplified by the study of circulant topologies showed an increase in the modeling rate, as well as the correctness and usefulness of such a model for various applications.