一种高效的可重构图像压缩体系结构

2007 International Conference on Signal Processing, Communications and Networking Pub Date : 2007-11-05 DOI:10.1109/ICSCN.2007.350743

D.U. Perumal, Shylendra Kumar, S. Prasanth, P. Kumar, M. Kannan, V. Vaidehi

{"title":"一种高效的可重构图像压缩体系结构","authors":"D.U. Perumal, Shylendra Kumar, S. Prasanth, P. Kumar, M. Kannan, V. Vaidehi","doi":"10.1109/ICSCN.2007.350743","DOIUrl":null,"url":null,"abstract":"This paper describes the development of a novel image compression architecture on runtime reconfigurable FPGAs. The partially reconfigurable discrete cosine transform architecture (PRDCT) is implemented by creating a difference bit stream between two possible architectures using flexible multiplier and accumulator (MAC) units. The non-reconfigurable modules make use of a multiplexed bus system to communicate with the reconfigurable modules. This scheme helps the user achieve significant reduction in area and power during run-time","PeriodicalId":257948,"journal":{"name":"2007 International Conference on Signal Processing, Communications and Networking","volume":"27 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-11-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"An Efficient Reconfigurable Image Compression Architecture\",\"authors\":\"D.U. Perumal, Shylendra Kumar, S. Prasanth, P. Kumar, M. Kannan, V. Vaidehi\",\"doi\":\"10.1109/ICSCN.2007.350743\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the development of a novel image compression architecture on runtime reconfigurable FPGAs. The partially reconfigurable discrete cosine transform architecture (PRDCT) is implemented by creating a difference bit stream between two possible architectures using flexible multiplier and accumulator (MAC) units. The non-reconfigurable modules make use of a multiplexed bus system to communicate with the reconfigurable modules. This scheme helps the user achieve significant reduction in area and power during run-time\",\"PeriodicalId\":257948,\"journal\":{\"name\":\"2007 International Conference on Signal Processing, Communications and Networking\",\"volume\":\"27 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-11-05\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 International Conference on Signal Processing, Communications and Networking\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICSCN.2007.350743\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 International Conference on Signal Processing, Communications and Networking","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSCN.2007.350743","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

本文介绍了一种基于运行时可重构fpga的新型图像压缩体系结构的开发。部分可重构的离散余弦变换架构(PRDCT)是通过使用灵活的乘法器和累加器(MAC)单元在两种可能的架构之间创建一个差分比特流来实现的。非可重构模块利用多路总线系统与可重构模块通信。该方案可帮助用户在运行期间显著减少面积和功耗

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An Efficient Reconfigurable Image Compression Architecture

This paper describes the development of a novel image compression architecture on runtime reconfigurable FPGAs. The partially reconfigurable discrete cosine transform architecture (PRDCT) is implemented by creating a difference bit stream between two possible architectures using flexible multiplier and accumulator (MAC) units. The non-reconfigurable modules make use of a multiplexed bus system to communicate with the reconfigurable modules. This scheme helps the user achieve significant reduction in area and power during run-time

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2007 International Conference on Signal Processing, Communications and Networking

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