信号完整性因素在高速多板测试设置

Sandeep Dattaprasad, Kyaw Swa Maung, K. Lew, Y. F. Lai, M. Y. Chong, M. K. Dey
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引用次数: 1

摘要

在存储技术中使用的混合信号片上系统(SoC)设计有了快速的改进,如SATA 6G(串行高级技术附件),SAS 6G(串行附加小型计算机系统接口),USB 3(通用串行总线)和DDR2/3(双数据速率)等存储设备。这类产品的设计趋向于减小印制电路板组件(PCBA)的尺寸。开发这种用于存储产品的高速pcb需要进行功能和其他参数测试,需要专门的测试平台。这种测试平台通常是多板系统,系统中的每块板都有高度复杂的器件,对各种信号完整性因素都很敏感。本文介绍了在设计此类系统时需要考虑的几个重要因素。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Signal integrity factors in high speed multi-board test setup
There has been rapid improvement in mixed signal System on Chip (SoC) designs used in storage technologies with high-speed interfaces such as SATA 6G (Serial Advanced Technology Attachment), SAS 6G (Serial Attached Small Computer System Interface), USB 3 (Universal Serial Bus), and memory devices such as DDR2/3 (Double Data Rate). The design of such products is trending towards reduction in size of Printed Circuit Board Assemblies (PCBA) used. Development of such high speed PCBAs for storage products requires performing functional and other parametric tests for which special test platforms are needed. Such test platforms are often multi-board systems with each board in the system having highly complex devices that are sensitive to various signal integrity factors. This paper presents few of the important factors that are to be considered while designing such systems.
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