{"title":"用于计算最大主成分的低功耗模拟芯片","authors":"F. Salam, S. Vedula, G. Erten","doi":"10.1109/ICNN.1994.375042","DOIUrl":null,"url":null,"abstract":"Test results of two prototype circuit implementations that compute the maximal principal component are described. The implementations are designed to be compact and operate in the subthreshold regime for low power consumption. The prototypes use direct realization of a nonlinear self-learning circuit models which we have developed.<<ETX>>","PeriodicalId":209128,"journal":{"name":"Proceedings of 1994 IEEE International Conference on Neural Networks (ICNN'94)","volume":"41 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-06-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Low power analog chips for the computation of the maximal principal component\",\"authors\":\"F. Salam, S. Vedula, G. Erten\",\"doi\":\"10.1109/ICNN.1994.375042\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Test results of two prototype circuit implementations that compute the maximal principal component are described. The implementations are designed to be compact and operate in the subthreshold regime for low power consumption. The prototypes use direct realization of a nonlinear self-learning circuit models which we have developed.<<ETX>>\",\"PeriodicalId\":209128,\"journal\":{\"name\":\"Proceedings of 1994 IEEE International Conference on Neural Networks (ICNN'94)\",\"volume\":\"41 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-06-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1994 IEEE International Conference on Neural Networks (ICNN'94)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICNN.1994.375042\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE International Conference on Neural Networks (ICNN'94)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICNN.1994.375042","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Low power analog chips for the computation of the maximal principal component
Test results of two prototype circuit implementations that compute the maximal principal component are described. The implementations are designed to be compact and operate in the subthreshold regime for low power consumption. The prototypes use direct realization of a nonlinear self-learning circuit models which we have developed.<>