{"title":"低功耗10位SAR ADC的集成电路EDA设计","authors":"Dan Bu, N. Wu, C. Qiu, Junbo Wang","doi":"10.1109/ICCT.2010.5688923","DOIUrl":null,"url":null,"abstract":"A 10-bit 1Ms/ps SAR ADC with low power is designed by integrated circuit EDA software, which is realized in a 0.18um CMOS process. The design combines a capacitor DAC, a CMOS dynamic comparator, a SAR digital logic control cell, and a two phase non-overlap clk cell. Through the EDA simulation results, the SAR ADC designed in this paper is suited for low power operation with 30.3 uW from a 1.8V voltage supply, and the input range is rail to rail‥1","PeriodicalId":253478,"journal":{"name":"2010 IEEE 12th International Conference on Communication Technology","volume":"66 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"Integrated circuit EDA design of 10-bit SAR ADC with low power\",\"authors\":\"Dan Bu, N. Wu, C. Qiu, Junbo Wang\",\"doi\":\"10.1109/ICCT.2010.5688923\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 10-bit 1Ms/ps SAR ADC with low power is designed by integrated circuit EDA software, which is realized in a 0.18um CMOS process. The design combines a capacitor DAC, a CMOS dynamic comparator, a SAR digital logic control cell, and a two phase non-overlap clk cell. Through the EDA simulation results, the SAR ADC designed in this paper is suited for low power operation with 30.3 uW from a 1.8V voltage supply, and the input range is rail to rail‥1\",\"PeriodicalId\":253478,\"journal\":{\"name\":\"2010 IEEE 12th International Conference on Communication Technology\",\"volume\":\"66 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 IEEE 12th International Conference on Communication Technology\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICCT.2010.5688923\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 IEEE 12th International Conference on Communication Technology","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCT.2010.5688923","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
利用集成电路EDA软件设计了一个低功耗的10位1Ms/ps SAR ADC，并在0.18um CMOS工艺上实现。该设计结合了电容DAC、CMOS动态比较器、SAR数字逻辑控制单元和两相不重叠时钟单元。通过EDA仿真结果可知，本文设计的SAR ADC适合于1.8V电压供电时30.3 uW的低功率工作，输入范围为轨到轨
Integrated circuit EDA design of 10-bit SAR ADC with low power
A 10-bit 1Ms/ps SAR ADC with low power is designed by integrated circuit EDA software, which is realized in a 0.18um CMOS process. The design combines a capacitor DAC, a CMOS dynamic comparator, a SAR digital logic control cell, and a two phase non-overlap clk cell. Through the EDA simulation results, the SAR ADC designed in this paper is suited for low power operation with 30.3 uW from a 1.8V voltage supply, and the input range is rail to rail‥1
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