A supply-noise-rejection technique in ADPLL with noise-cancelling current source

We propose a supply noise rejection technique, which is applied to an all-digital phase-locked loop (ADPLL). Supply noise is cancelled by adding a cancellation current whose fluctuation is the same as that of a supply-noise component in an oscillator current. The proposed technique is realized with a small area and current dissipation, and is tolerant to process, voltage, and temperature (PVT) variations without calibration. The proof-of-concept chip was fabricated using a 65 nm CMOS technology. It was measured that the peak-to-peak jitter was reduced by 54 % in the presence of 30 mVpp, 15 MHz supply noise, and the robustness of the proposed technique was verified by the measurements.