一个1.3 GSample/s 10抽头全速率可变延迟自定时FIR滤波器与时钟接口

2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315) Pub Date : 2002-08-07 DOI:10.1109/ISSCC.2002.992938

J. Tierno, A. Rylyakov, S. Rylov, Montek Singh, P. Ampadu, S. Nowick, M. Immediato, S. Gowda

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引用次数: 11

摘要

6b 10分路数字FIR滤波器具有自定时数据路径、时钟接口和可变延迟。该滤波器的结构是全速率分布式算法，采用符号位偏移二进制(SDOB)数字表示。该0.45 mm/sup /电路采用0.18 μm CMOS工艺，工作电源范围为1.2 V至2.1 V，在300 MSample/s和4个周期时延下功耗为80mw，在1.3 GSample/s和7个周期时延下功耗为500mw。

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A 1.3 GSample/s 10-tap full-rate variable-latency self-timed FIR filter with clocked interfaces

A 6 b 10-tap digital FIR filter has a self-timed datapath, clocked interfaces, and variable latency. The architecture of the filter is full rate, distributed arithmetic with signed-digit offset binary (SDOB) number representation. The 0.45 mm/sup 2/ circuit, in 0.18 μm CMOS technology, is operational from 1.2 V to 2.1 V power supply, and has 80 mW dissipation at 300 MSample/s and 4 cycles of latency, and 500 mW at 1.3 GSample/s and 7 cycles of latency.

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2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315)

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