Optimal routing in the shuffle-exchange networks for multiprocessor systems

The authors propose the shuffle-exchange and exchange-unshuffle network and a combination routing scheme. They prove that combination routing is optimal for s/e&e/u interconnection networks in the sense that it leads to the lowest possible number of cycles through the single-stage for every pair of source and destination addresses. The authors design a systolic algorithm for calculating the parameters for carrying out combination routing. Using standard shuffle-exchange routing, the average network delay can not be less than log N even with various augmented hardware. Simulation experiments on the combination routing show that the average network delays are significantly less than log N.<>