用于混合精度深度学习推理处理器系统能耗降低20%的1w8r20t SRAM码本

2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS) Pub Date : 2023-06-11 DOI:10.1109/AICAS57966.2023.10168555

Ryotaro Ohara, Masaya Kabuto, Masakazu Taichi, Atsushi Fukunaga, Yuto Yasuda, Riku Hamabe, S. Izumi, H. Kawaguchi

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引用次数: 0

摘要

本研究介绍一种用于深度学习处理器码本量化的1w8r20t多端口存储器。我们在40 nm工艺中制造了存储器，并实现了存储器读取访问时间为2.75 ns和2.7 pj/byte的功耗。此外，我们使用NVIDIA的深度学习处理器NVDLA作为母题，并根据从实际提议的存储器中获得的功率进行模拟。得到的功率和面积分别降低20.24%和26.24%。

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A 1W8R 20T SRAM Codebook for 20% Energy Reduction in Mixed-Precision Deep-Learning Inference Processor System

This study introduces a 1W8R 20T multiport memory for codebook quantization in deep-learning processors. We manufactured the memory in a 40 nm process and achieved memory read-access time at 2.75 ns and 2.7-pj/byte power consumption. In addition, we used NVDLA, which was NVIDIA’s deep-learning processor, as a motif and simulated it based on the power obtained from the actual proposed memory. The obtained power and area reduction results are 20.24% and 26.24%, respectively.

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来源期刊

2023 IEEE 5th International Conference on Artificial Intelligence Circuits and Systems (AICAS)

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