Dynamic Reduction of Power Consumption in Direct-RF Sampling Receivers with Variable Decimation

The conventional direct radio frequency (RF) sampling receivers can not reduce their power consumption dynamically according to the power of input signals. The dynamic reduction enables them to decrease the total power consumption during operation to the level required for wireless terminals. We decrease the clock frequency of decimators in first-order recursive cascaded integrator-comb (CIC) filters after a time-interleaved ADC (TI-ADC) in a direct-RF sampling receiver, detecting higher power of input signals than the required sensitivity. Although the decimation slightly degrades the output signal-to-noise ratio (SNR) of the receiver, it reduces the power consumption of the digital building blocks. We design a 3.68-GS/s direct-RF sampling receiver, including analog and digital blocks, for Sub-GHz applications by using a 65-nm CMOS process. Simulations show that the receiver reduces a power consumption of 10.6 mW to 9.6 mW with a decimation factor of eight, whereas increasing the output SNR by 0.9 dB. This means that the receiver can decrease the power consumption, not degrading the output SNR, when receiving higher input power than the required level.