A Hardware Implementation for Acquisition Stage Based on the Parallel Frequency Search Method

The GPS-based navigation devices play a substantial role in modern life. The GPS receivers provide time, position, and velocity information which are crucial to precise and accurate navigation, especially in the aviation and marine industry. Due to the CDMA nature of the GPS signals, the acquisition and tracking stages are inseparable parts of a GPS receiver. Therefore, high efficiency, high speed, and accuracy are undeniable factors of a good receiver.In this paper, a hardware implementation of the acquisition stage is proposed and analyzed. This structure exploits the parallel frequency search method and utilizes the frequency domain simplifications through the Fourier transform. The structure is implemented and evaluated on the Xilinx ZedBoard which uses an XC7Z020 chip as the main processing unit. The structure's moderate resource usage has made it a good choice for a hardware implementation of GPS receiver.