在HDLs中支持系统级规范的特性

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference Pub Date : 1993-09-20 DOI:10.1109/EURDAC.1993.410689

Sanjiv Narayan, D. Gajski

{"title":"在HDLs中支持系统级规范的特性","authors":"Sanjiv Narayan, D. Gajski","doi":"10.1109/EURDAC.1993.410689","DOIUrl":null,"url":null,"abstract":"As synthesis tools become more advanced and reliable, the entry point for the designer in the design process is moving towards higher levels of specification. Issues related to the specification of embedded systems are discussed. The authors compare VHDL with five other specification languages: HardwareC, SDL (Specification and Description Language), Statecharts, SpecCharts, and CSP (Communicating Sequential Processes). The capabilities of these languages with respect to specifying designs at the system-level are highlighted. The authors conclude by presenting a list of features which are desirable in a language to be used for specifying systems.<<ETX>>","PeriodicalId":339176,"journal":{"name":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","volume":"155 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-09-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"24","resultStr":"{\"title\":\"Features supporting system-level specification in HDLs\",\"authors\":\"Sanjiv Narayan, D. Gajski\",\"doi\":\"10.1109/EURDAC.1993.410689\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As synthesis tools become more advanced and reliable, the entry point for the designer in the design process is moving towards higher levels of specification. Issues related to the specification of embedded systems are discussed. The authors compare VHDL with five other specification languages: HardwareC, SDL (Specification and Description Language), Statecharts, SpecCharts, and CSP (Communicating Sequential Processes). The capabilities of these languages with respect to specifying designs at the system-level are highlighted. The authors conclude by presenting a list of features which are desirable in a language to be used for specifying systems.<<ETX>>\",\"PeriodicalId\":339176,\"journal\":{\"name\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"volume\":\"155 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-09-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"24\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EURDAC.1993.410689\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EURDAC.1993.410689","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 24

摘要

随着合成工具变得更加先进和可靠，设计人员在设计过程中的切入点正朝着更高层次的规范发展。讨论了与嵌入式系统规范相关的问题。作者将VHDL与其他五种规范语言进行了比较:HardwareC, SDL(规范和描述语言)，Statecharts, SpecCharts和CSP(通信顺序进程)。强调了这些语言在系统级指定设计方面的能力。作者最后给出了一份语言中用于指定系统所需的特性列表

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

Features supporting system-level specification in HDLs

As synthesis tools become more advanced and reliable, the entry point for the designer in the design process is moving towards higher levels of specification. Issues related to the specification of embedded systems are discussed. The authors compare VHDL with five other specification languages: HardwareC, SDL (Specification and Description Language), Statecharts, SpecCharts, and CSP (Communicating Sequential Processes). The capabilities of these languages with respect to specifying designs at the system-level are highlighted. The authors conclude by presenting a list of features which are desirable in a language to be used for specifying systems.<>

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference

自引率

0.00%

发文量