Xian Yang Lim, Wu Cong Lim, Boon Chiat Terence Teo, V. Navaneethan, Chong Boon Tan, Nardi Utomo, L. Siek, A. Alvandpour
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This article discusses the design considerations of a current-steering digital-to-analogue converter (CSDAC) and reviews some techniques that addresses non-ideal behaviors of a CSDAC. To understand the design considerations and how non-idealities affect the performance of a CSDAC, a 12-bit CSDAC is designed in TSMC 40nm technology node and the simulation results are provided.
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