Ninita Geddam, S. B, Adhithan Pon, A. Bhattacharyya, R. R.
{"title":"温度对大功率应用p-GaN HEMT的影响","authors":"Ninita Geddam, S. B, Adhithan Pon, A. Bhattacharyya, R. R.","doi":"10.1109/ICDCS48716.2020.243569","DOIUrl":null,"url":null,"abstract":"In this work, we study the influence of temperature on the p-GaN gate (with/without spacer) enhancement mode HEMT. First, the HEMT structure is designed with a p-type gate and its DC characteristics have been studied at room temperature (RT). It is observed that on-current increases significantly (1.2 times high) when the spacer layer is removed. The influence of temperature variation has been analysed in both the devices in terms of on-current (Id), leakage current (Ioff), threshold voltage (Vt) and on-resistance (Ron). Our simulation results show that the without spacer layer p-GaN gate HEMT enhances the device performance for various temperatures.","PeriodicalId":307218,"journal":{"name":"2020 5th International Conference on Devices, Circuits and Systems (ICDCS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Influence of Temperature on p-GaN HEMT for High Power Application\",\"authors\":\"Ninita Geddam, S. B, Adhithan Pon, A. Bhattacharyya, R. R.\",\"doi\":\"10.1109/ICDCS48716.2020.243569\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this work, we study the influence of temperature on the p-GaN gate (with/without spacer) enhancement mode HEMT. First, the HEMT structure is designed with a p-type gate and its DC characteristics have been studied at room temperature (RT). It is observed that on-current increases significantly (1.2 times high) when the spacer layer is removed. The influence of temperature variation has been analysed in both the devices in terms of on-current (Id), leakage current (Ioff), threshold voltage (Vt) and on-resistance (Ron). Our simulation results show that the without spacer layer p-GaN gate HEMT enhances the device performance for various temperatures.\",\"PeriodicalId\":307218,\"journal\":{\"name\":\"2020 5th International Conference on Devices, Circuits and Systems (ICDCS)\",\"volume\":\"40 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-03-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 5th International Conference on Devices, Circuits and Systems (ICDCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICDCS48716.2020.243569\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 5th International Conference on Devices, Circuits and Systems (ICDCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICDCS48716.2020.243569","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Influence of Temperature on p-GaN HEMT for High Power Application
In this work, we study the influence of temperature on the p-GaN gate (with/without spacer) enhancement mode HEMT. First, the HEMT structure is designed with a p-type gate and its DC characteristics have been studied at room temperature (RT). It is observed that on-current increases significantly (1.2 times high) when the spacer layer is removed. The influence of temperature variation has been analysed in both the devices in terms of on-current (Id), leakage current (Ioff), threshold voltage (Vt) and on-resistance (Ron). Our simulation results show that the without spacer layer p-GaN gate HEMT enhances the device performance for various temperatures.