{"title":"基于广义d算法的组合多值网络测试模式生成","authors":"V. Shmerko, S. Yanushkevich, V. Levashenko","doi":"10.1109/ISMVL.1997.601388","DOIUrl":null,"url":null,"abstract":"A calculus for test pattern generation for Multi-Valued Logic (MVL) networks using so-called Direct D-cubes (DD-cubes) is proposed. The concept of the DD-cubes is introduced based on Direct Logic Derivatives generated by a matrix algorithm. It provides a means to support the central stages of test generating on parallel hardware, for instance, linear systolic arrays.","PeriodicalId":206024,"journal":{"name":"Proceedings 1997 27th International Symposium on Multiple- Valued Logic","volume":"46 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-05-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Test pattern generation for combinatorial multi-valued networks based on generalized D-algorithm\",\"authors\":\"V. Shmerko, S. Yanushkevich, V. Levashenko\",\"doi\":\"10.1109/ISMVL.1997.601388\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A calculus for test pattern generation for Multi-Valued Logic (MVL) networks using so-called Direct D-cubes (DD-cubes) is proposed. The concept of the DD-cubes is introduced based on Direct Logic Derivatives generated by a matrix algorithm. It provides a means to support the central stages of test generating on parallel hardware, for instance, linear systolic arrays.\",\"PeriodicalId\":206024,\"journal\":{\"name\":\"Proceedings 1997 27th International Symposium on Multiple- Valued Logic\",\"volume\":\"46 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-05-28\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 1997 27th International Symposium on Multiple- Valued Logic\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.1997.601388\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 1997 27th International Symposium on Multiple- Valued Logic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.1997.601388","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Test pattern generation for combinatorial multi-valued networks based on generalized D-algorithm
A calculus for test pattern generation for Multi-Valued Logic (MVL) networks using so-called Direct D-cubes (DD-cubes) is proposed. The concept of the DD-cubes is introduced based on Direct Logic Derivatives generated by a matrix algorithm. It provides a means to support the central stages of test generating on parallel hardware, for instance, linear systolic arrays.