{"title":"采用差分开关反馈的10gb /s CMOS超高速金码发生器","authors":"C.‐L. Lu, H.-C. Wang, J. Juang, H. Chuang","doi":"10.1109/EMICC.2007.4412693","DOIUrl":null,"url":null,"abstract":"This paper proposes a new architecture for the implementation of an n-input XOR gate in ultrahigh-speed applications. The new circuitry makes it possible to let the conventional sequence logic with XOR feedback, such as Gold code generator, to work up to ten-gigabit per second. This paper will systematically describe the principle of substituting a set of differential switches for an XOR gate. The proposed circuitry is demonstrated in a five-stage Gold code generator implemented in TSMC 0.18-mum 1P6M CMOS process. The simulation results show that the delay of the proposed four-input XOR gate is so much improved as to let the five-stage (5,3) and (5,4,3,2) Gold code generator to work up to 10 Gb/s.","PeriodicalId":436391,"journal":{"name":"2007 European Microwave Integrated Circuit Conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-12-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"10-Gb/s CMOS ultrahigh-speed gold-code generator using differential-switches feedback\",\"authors\":\"C.‐L. Lu, H.-C. Wang, J. Juang, H. Chuang\",\"doi\":\"10.1109/EMICC.2007.4412693\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper proposes a new architecture for the implementation of an n-input XOR gate in ultrahigh-speed applications. The new circuitry makes it possible to let the conventional sequence logic with XOR feedback, such as Gold code generator, to work up to ten-gigabit per second. This paper will systematically describe the principle of substituting a set of differential switches for an XOR gate. The proposed circuitry is demonstrated in a five-stage Gold code generator implemented in TSMC 0.18-mum 1P6M CMOS process. The simulation results show that the delay of the proposed four-input XOR gate is so much improved as to let the five-stage (5,3) and (5,4,3,2) Gold code generator to work up to 10 Gb/s.\",\"PeriodicalId\":436391,\"journal\":{\"name\":\"2007 European Microwave Integrated Circuit Conference\",\"volume\":\"96 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-12-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 European Microwave Integrated Circuit Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EMICC.2007.4412693\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 European Microwave Integrated Circuit Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EMICC.2007.4412693","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
摘要
本文提出了一种在超高速应用中实现n输入异或门的新架构。新的电路使传统的异或反馈序列逻辑(如Gold代码生成器)能够以每秒10gb的速度工作。本文将系统地描述用一组差动开关代替异或门的原理。该电路在台积电0.18 μ m 1P6M CMOS工艺中实现的五级金码发生器中进行了演示。仿真结果表明,所提出的四输入异或门的延迟得到了很大的改善,使得五级(5,3)和(5,4,3,2)金码发生器的工作速度高达10gb /s。
10-Gb/s CMOS ultrahigh-speed gold-code generator using differential-switches feedback
This paper proposes a new architecture for the implementation of an n-input XOR gate in ultrahigh-speed applications. The new circuitry makes it possible to let the conventional sequence logic with XOR feedback, such as Gold code generator, to work up to ten-gigabit per second. This paper will systematically describe the principle of substituting a set of differential switches for an XOR gate. The proposed circuitry is demonstrated in a five-stage Gold code generator implemented in TSMC 0.18-mum 1P6M CMOS process. The simulation results show that the delay of the proposed four-input XOR gate is so much improved as to let the five-stage (5,3) and (5,4,3,2) Gold code generator to work up to 10 Gb/s.