FPGA Based Symmetric Multi-core Processors for Optimized Performance of H.264 Encoder

Digital video technology is burgeoning new standards broadening the gamut of prerequisites such as high definition video quality and more resolution substantially at lower bit rates than previous standards. Among the latest video compression algorithms, the newly established H.264 standard has become increasingly popular. However, the high coding efficiency of it comes at the cost of increase in computational complexity which makes the real-time implementation a great challenge. Previous works in video compression implement a dual core DSP processor executing this composite H.264 algorithm in parts, but has certain bottlenecks like timing, reliability and efficiency with a small overhead of synchronization. With higher interprocessor bus speeds, streamlined memory and a highly programmable FPGA multi-core architecture the limitations of current platforms based on DSPs and ASICs can be overwhelmed. This paper presents an FPGA based multicore processor implementation to optimize the H.264 encoder performance between the cores providing scalability, attaining load balance among the cores and parallel execution reducing the dependability of resources. This enables a more effectual use of processing power of the cores.