异构处理器的功率建模

Tahir Diop, Natalie D. Enright Jerger, J. Anderson
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引用次数: 14

摘要

随着功率成为越来越重要的设计考虑因素,在设计过程的各个阶段都需要精确的功率模型。虽然功率模型可用于cpu和gpu,但只有简单模型可用于异构处理器。我们提出了一种基于微基准的建模技术,可用于芯片多处理器(cmp)和加速处理单元(apu)。我们使用我们的方法来模拟英特尔至强CPU和AMD Fusion异构处理器的功率。至强处理器模型的错误率低于3%,而Fusion的错误率仅为7%。我们还提出了一种方法来减少创建这些模型所需的基准测试的数量。我们没有针对每种因素组合(例如不同的操作或内存访问模式)运行微基准测试,而是对类似的微基准测试进行聚类,以避免不必要的模拟。我们表明,有可能消除多达93%的计算微基准测试,同时仍然产生错误率低于10%的功率模型。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Power Modeling for Heterogeneous Processors
As power becomes an ever more important design consideration, there is a need for accurate power models at all stages of the design process. While power models are available for CPUs and GPUs, only simple models are available for heterogeneous processors. We present a micro-benchmark-based modeling technique that can be used for chip multiprocessor (CMPs) and accelerated processing units (APUs). We use our approach to model power on an Intel Xeon CPU and an AMD Fusion heterogeneous processor. The resulting error rate for the Xeon's model is below 3% and is only 7% for the Fusion. We also present a method to reduce the number of benchmarks required to create these models. Instead of running micro-benchmarks for every combination of factors (e.g. different operations or memory access patterns), we cluster similar micro-benchmarks to avoid unnecessary simulations. We show that it is possible to eliminate as many as 93% of the compute micro-benchmarks, while still producing power models having less than 10% error rate.
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