现代体系结构中原子原语的性能建模

F. Hoseini, A. Atalar, P. Tsigas
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引用次数: 5

摘要

利用处理器的原子原语以原子方式访问内存位置是并行软件系统正确性和可行性的关键。原子性能在并行软件系统的可伸缩性和整体性能中起着重要的作用。在这项工作中,我们从延迟、吞吐量、公平性、能耗等方面研究了原子原语在两种常见软件执行设置上下文中的性能,这两种设置会导致共享内存上的高争用访问和低争用访问。我们对这两个应用程序上下文中的原子性能进行了详尽的研究,并提出了一个捕获其行为的性能模型。我们考虑两种最先进的架构:Intel Xeon E5和Xeon Phi (KNL)。我们提出了一个模型,该模型以在这些共享缓存线上执行原子原语的线程之间的缓存线反弹为中心。该模型在实践中使用非常简单,可以准确地捕获这些执行场景下原子的行为,并有助于多线程编程中的算法设计决策。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Modeling the Performance of Atomic Primitives on Modern Architectures
Utilizing the atomic primitives of a processor to access a memory location atomically is key to the correctness and feasibility of parallel software systems. The performance of atomics plays a significant role in the scalability and overall performance of parallel software systems. In this work, we study the performance -in terms of latency, throughput, fairness, energy consumption- of atomic primitives in the context of the two common software execution settings that result in high and low contention access on shared memory. We perform and present an exhaustive study of the performance of atomics in these two application contexts and propose a performance model that captures their behavior. We consider two state-of-the-art architectures: Intel Xeon E5, Xeon Phi (KNL). We propose a model that is centered around the bouncing of cache lines between threads that execute atomic primitives on these shared cache lines. The model is very simple to be used in practice and captures the behavior of atomics accurately under these execution scenarios and facilitate algorithmic design decisions in multi-threaded programming.
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