L. DeBrunner, S.A. Ahmed, V. DeBrunner, W.D. Ballew
{"title":"一个完全流水线化的正则数组处理器实现的RITE算法","authors":"L. DeBrunner, S.A. Ahmed, V. DeBrunner, W.D. Ballew","doi":"10.1109/ACSSC.1993.342626","DOIUrl":null,"url":null,"abstract":"The paper presents a completely pipelined regular array processor implementation of a direction of arrival estimator. The estimator employs the recursive/iterative eigenspace decomposition (RITE) of a hermitian Toeplitz spatial correlation matrix. In addition to the recursive and iterative nature of the algorithm, various dependencies are strongly connected. The eigenvalue computations are based on the secular equation, and the eigenvector computations are based on the Schur algorithm. A new concept of a flushing processor is employed to integrate the Schur implementation of lower and upper triangular matrices with asymptotic processor efficiency of 100%.<<ETX>>","PeriodicalId":266447,"journal":{"name":"Proceedings of 27th Asilomar Conference on Signals, Systems and Computers","volume":"11 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1993-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A completely pipelined regular array processor implementation of the RITE algorithm\",\"authors\":\"L. DeBrunner, S.A. Ahmed, V. DeBrunner, W.D. Ballew\",\"doi\":\"10.1109/ACSSC.1993.342626\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The paper presents a completely pipelined regular array processor implementation of a direction of arrival estimator. The estimator employs the recursive/iterative eigenspace decomposition (RITE) of a hermitian Toeplitz spatial correlation matrix. In addition to the recursive and iterative nature of the algorithm, various dependencies are strongly connected. The eigenvalue computations are based on the secular equation, and the eigenvector computations are based on the Schur algorithm. A new concept of a flushing processor is employed to integrate the Schur implementation of lower and upper triangular matrices with asymptotic processor efficiency of 100%.<<ETX>>\",\"PeriodicalId\":266447,\"journal\":{\"name\":\"Proceedings of 27th Asilomar Conference on Signals, Systems and Computers\",\"volume\":\"11 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1993-11-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 27th Asilomar Conference on Signals, Systems and Computers\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ACSSC.1993.342626\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 27th Asilomar Conference on Signals, Systems and Computers","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ACSSC.1993.342626","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A completely pipelined regular array processor implementation of the RITE algorithm
The paper presents a completely pipelined regular array processor implementation of a direction of arrival estimator. The estimator employs the recursive/iterative eigenspace decomposition (RITE) of a hermitian Toeplitz spatial correlation matrix. In addition to the recursive and iterative nature of the algorithm, various dependencies are strongly connected. The eigenvalue computations are based on the secular equation, and the eigenvector computations are based on the Schur algorithm. A new concept of a flushing processor is employed to integrate the Schur implementation of lower and upper triangular matrices with asymptotic processor efficiency of 100%.<>