基于CMOS、PTL和GDI的布朗乘法器在信号处理中的性能分析

M. Basha, Srinivasulu Gundala, G. Kumar
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引用次数: 3

摘要

功率、速度和面积是计算应用和便携电子设备信号处理的关键设计限制。乘法器在数字系统中高效节能的信号处理应用中起着重要的作用。通过二进制乘法可以有效地得到大位数的乘积。提出了一种基于栅极扩散输入(GDI)的低功耗高速布朗乘法器,改进了行、列旁通方案。从仿真结果可以看出,基于GDI的布朗乘法器,采用CMOS等方法节能4%以上,节能99%以上;采用行、列旁路技术,采用CMOS等方法节能15%以上,节能30%以上。从布局上,还分析了GDI博朗乘法器比CMOS及其其他对应部件的面积效率高,与基于通晶体管逻辑(PTL)的列和行旁通技术相比,面积增加了9%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Performance Analysis of CMOS, PTL and GDI Based Braun Multiplier for Signal Processing Applications
Power, speed and area are key design constraints in signal processing for computing applications as well as for handy electronic gadgets. Multiplier plays a significant role in energy efficient signal processing applications in digital systems. Product of large bit numbers occurs efficiently through binary multiplication. A low power and high speed Gate Diffusion Input (GDI) based Braun multiplier with improved row and column bypassing scheme is presented in this paper. From the simulated results, it is observed that, the GDI based Braun multiplier achieves energy savings more than 4% and up to 99% with CMOS and other methods and in the same way EDP savings more than 15% and up to 30% with CMOS and other methods by means of column and row bypassing techniques. From the layout, it is also analyzed that, GDI Braun multiplier is area efficient over CMOS and its other counter parts at the penalty of 9% more area in comparison with pass transistor logic (PTL) based column and row bypassing techniques.
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