7.9 fj /转换步长8-b 400-MS/s每周期2-b SAR ADC，带有预设电容DAC

2013 IEEE 10th International Conference on ASIC Pub Date : 2013-10-01 DOI:10.1109/ASICON.2013.6812049

Jixuan Xiang, Jian Mei, Hao-Hsuan Chang, Fan Ye

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引用次数: 1

摘要

本文提出了一种8-b 400-MS/s的2-b /周期SAR ADC，并在65nm CMOS工艺中进行了仿真。该SAR ADC实现了快速转换速率和低功耗，在400 ms /s采样率和186MHz输入信号下，SNDR为48.9dB, SFDR为57.8dB, ENOB为7.83位。ADC功耗为0.766mW, FoM为7.9fJ/转换步长，采样率为400 ms /s，电源电压为1.2 v。

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A 7.9-fJ/conversion-step 8-b 400-MS/s 2-b-per-cycle SAR ADC with A preset capacitive DAC

This paper presents an 8-b 400-MS/s 2-b-per-cycle SAR ADC with a preset capacitive DAC, which is simulated in 65-nm CMOS process. This SAR ADC achieves rapid conversion rate and low power, leading SNDR to 48.9dB, SFDR to 57.8dB, and ENOB to 7.83 bits at 400-MS/s sampling rate and in 186MHz input signal. The ADC consumes 0.766mW, and the FoM is 7.9fJ/conversion-step at 400-MS/s sampling rate from a 1.2-V supply voltage.

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2013 IEEE 10th International Conference on ASIC

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