用于InP misfet的ecr等离子体沉积栅介电体

A. Fathimulla, D. Gutierrez
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引用次数: 0

摘要

研究了不同沉积参数下SiO/sub 2/和Si/sub 3/N/sub 4/薄膜的性能,以及SiO/sub 2/栅极介质下InP金属绝缘半导体场效应管(MISFET)的性能。实验在Astex微波源的等离子体Therm SLR 770 ECR系统中进行。采用Si衬底和未掺杂的InP衬底对薄膜的质量进行了研究。用ecr沉积SiO/ sub2 /制备的InP MISFET表现出与使用其他沉积栅介电体技术制备的MISFET相同或更好的直流特性和漏极电流漂移。结果表明,ecr沉积膜是栅极介质和III-V器件钝化的理想候选材料。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
ECR-plasma-deposited gate dielectrics for InP MISFETs
The authors present the properties of SiO/sub 2/ and Si/sub 3/N/sub 4/ films for various deposition parameters and the performance of an InP metal-insulated semiconductor FET (MISFET) with a SiO/sub 2/ gate dielectric. The experiments were performed in a Plasma Therm SLR 770 ECR system with an Astex microwave source. Both Si and undoped InP substrates were used to study the quality of the films. The InP MISFET fabricated with the ECR-deposited SiO/sub 2/ exhibited DC characteristics and drain current drift as good or better than those of MISFETs fabricated using other techniques for depositing gate dielectrics. The results indicate that the ECR-deposited films are excellent candidates for gate dielectrics and passivation of III-V devices.<>
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