F. Pellizzer, A. Pirovano, F. Ottogalli, M. Magistretti, M. Scaravaggi, P. Zuliani, M. Tosi, Augusto Benvenuti, P. Besana, S. Cadeo, T. Marangon, R. Morandi, R. Piva, A. Spandre, R. Zonca, Alberto Modelli, E. Varesi, T. Lowrey, A. L. Lacaita, G. Casagrande, P. Cappelletti, R. Bez
{"title":"用于嵌入式和独立非易失性存储器应用的新型/spl μ /沟槽相变存储器单元","authors":"F. Pellizzer, A. Pirovano, F. Ottogalli, M. Magistretti, M. Scaravaggi, P. Zuliani, M. Tosi, Augusto Benvenuti, P. Besana, S. Cadeo, T. Marangon, R. Morandi, R. Piva, A. Spandre, R. Zonca, Alberto Modelli, E. Varesi, T. Lowrey, A. L. Lacaita, G. Casagrande, P. Cappelletti, R. Bez","doi":"10.1109/VLSIT.2004.1345368","DOIUrl":null,"url":null,"abstract":"A novel cell structure for chalcogenide-based non-volatile Phase-Change Memories is presented. The new /spl mu/trench approach is fully compatible with an advanced CMOS technology, is highly manufacturable and allows to optimize array density and cell performance. Programming currents of 600 /spl mu/A, endurance of 10/sup 11/ programming cycles and data retention capabilities for 10 years at 110/spl deg/C have been demonstrated. The manufacturability is proven by experimental results from multi-megabit arrays.","PeriodicalId":297052,"journal":{"name":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","volume":"47 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"157","resultStr":"{\"title\":\"Novel /spl mu/trench phase-change memory cell for embedded and stand-alone non-volatile memory applications\",\"authors\":\"F. Pellizzer, A. Pirovano, F. Ottogalli, M. Magistretti, M. Scaravaggi, P. Zuliani, M. Tosi, Augusto Benvenuti, P. Besana, S. Cadeo, T. Marangon, R. Morandi, R. Piva, A. Spandre, R. Zonca, Alberto Modelli, E. Varesi, T. Lowrey, A. L. Lacaita, G. Casagrande, P. Cappelletti, R. Bez\",\"doi\":\"10.1109/VLSIT.2004.1345368\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A novel cell structure for chalcogenide-based non-volatile Phase-Change Memories is presented. The new /spl mu/trench approach is fully compatible with an advanced CMOS technology, is highly manufacturable and allows to optimize array density and cell performance. Programming currents of 600 /spl mu/A, endurance of 10/sup 11/ programming cycles and data retention capabilities for 10 years at 110/spl deg/C have been demonstrated. The manufacturability is proven by experimental results from multi-megabit arrays.\",\"PeriodicalId\":297052,\"journal\":{\"name\":\"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.\",\"volume\":\"47 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-06-15\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"157\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSIT.2004.1345368\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSIT.2004.1345368","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Novel /spl mu/trench phase-change memory cell for embedded and stand-alone non-volatile memory applications
A novel cell structure for chalcogenide-based non-volatile Phase-Change Memories is presented. The new /spl mu/trench approach is fully compatible with an advanced CMOS technology, is highly manufacturable and allows to optimize array density and cell performance. Programming currents of 600 /spl mu/A, endurance of 10/sup 11/ programming cycles and data retention capabilities for 10 years at 110/spl deg/C have been demonstrated. The manufacturability is proven by experimental results from multi-megabit arrays.