{"title":"一个1.3V-1.8V可配置锁相环与自适应电荷泵","authors":"S. Jandhyala, Soumya Tapse","doi":"10.1109/DISCOVER.2016.7806236","DOIUrl":null,"url":null,"abstract":"In this manuscript, we propose a robust phase locked loop (PLL) using an adaptive, low current-mismatch charge pump in 180nm UMC MPW RF process targeted for internet of things (IoT) applications. The PLL operates over a supply voltage range of 1.3V-1.8V, generating locking frequencies in the range 500 MHz to 1.5 GHz. The proposed charge pump limits the variation in charging and discharging currents to 0.03% of its biasing value, which is designed to be 34.7uA, for change in control voltage from 0.4 V to 1.1 V. Power consumption of the PLL is limited to 2.3mW at 1.8V supply voltage and reduces to 0.9mW for a supply voltage of 1.3V. A 10bit successive approximation register analog to digital converter (SAR ADC) is operated using the proposed PLL and the effect of variation in frequency on its output is demonstrated.","PeriodicalId":383554,"journal":{"name":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 1.3V–1.8V configurable phase locked loop with an adaptive charge pump\",\"authors\":\"S. Jandhyala, Soumya Tapse\",\"doi\":\"10.1109/DISCOVER.2016.7806236\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this manuscript, we propose a robust phase locked loop (PLL) using an adaptive, low current-mismatch charge pump in 180nm UMC MPW RF process targeted for internet of things (IoT) applications. The PLL operates over a supply voltage range of 1.3V-1.8V, generating locking frequencies in the range 500 MHz to 1.5 GHz. The proposed charge pump limits the variation in charging and discharging currents to 0.03% of its biasing value, which is designed to be 34.7uA, for change in control voltage from 0.4 V to 1.1 V. Power consumption of the PLL is limited to 2.3mW at 1.8V supply voltage and reduces to 0.9mW for a supply voltage of 1.3V. A 10bit successive approximation register analog to digital converter (SAR ADC) is operated using the proposed PLL and the effect of variation in frequency on its output is demonstrated.\",\"PeriodicalId\":383554,\"journal\":{\"name\":\"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)\",\"volume\":\"50 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/DISCOVER.2016.7806236\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DISCOVER.2016.7806236","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.3V–1.8V configurable phase locked loop with an adaptive charge pump
In this manuscript, we propose a robust phase locked loop (PLL) using an adaptive, low current-mismatch charge pump in 180nm UMC MPW RF process targeted for internet of things (IoT) applications. The PLL operates over a supply voltage range of 1.3V-1.8V, generating locking frequencies in the range 500 MHz to 1.5 GHz. The proposed charge pump limits the variation in charging and discharging currents to 0.03% of its biasing value, which is designed to be 34.7uA, for change in control voltage from 0.4 V to 1.1 V. Power consumption of the PLL is limited to 2.3mW at 1.8V supply voltage and reduces to 0.9mW for a supply voltage of 1.3V. A 10bit successive approximation register analog to digital converter (SAR ADC) is operated using the proposed PLL and the effect of variation in frequency on its output is demonstrated.