Design of Ultra Low Power, Area Efficient Ring Counter Based SAR ADC

We have discussed about counter-based SAR ADC in this research paper. A significant component of the high-speed application of ADCs is the SARs critical path. ADCs needed for long term and battery-operated applications typically consume relatively less power. Applications requiring low power, moderate resolution, and medium speed is best suited for SAR ADC. Dynamic latch is employed in our ADC to boost performance and achieve low power consumption. We have demonstrated a 45nm CMOS-simulated, 4-bit low power SAR ADC. Utilizing an ADC design with the maximum amount of simplification, which consists of a dynamic latch comparator, in this paper we are primarily focusing on increasing the sampling frequency of the SAR ADC in order to get high conversion rate. The continuous time analogue low pass filter, which is typically used in front of the ADC to avoid aliasing, was also explored in this paper. Active-RC filters and operational transconductance-C filters are investigated and developed. Results from simulations and measurements are offered to illustrate the performance and functionality.