片上网络仿真的建模方式分析

NORCHIP 2010 Pub Date : 2010-12-17 DOI:10.1109/NORCHIP.2010.5669448

Lasse Lehtonen, E. Salminen, T. Hamalainen

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引用次数: 6

摘要

本文分析了用SystemC编写的片上网络(NoC)模型对仿真速度的影响。将两种寄存器传输级(RTL)模型和近似定时(AT)和松散定时(LT)事务级(TL)模型与参考RTL VHDL二维网格模型进行了比较。使用商业模拟器和OSCI SystemC参考内核评估了三种不同的网格尺寸。所研究的AT模型在10%的估计误差下实现了13 - 40倍的加速。

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Analysis of modeling styles on Network-on-Chip simulation

This paper analyses the effects of Network-on-Chip (NoC) models written in SystemC on simulation speed. Two Register Transfer Level (RTL) models and Approximately Timed (AT) and Loosely Timed (LT) Transaction Level (TL) models are compared against reference RTL VHDL 2D mesh model. Three different mesh sizes are evaluated using a commercial simulator and OSCI SystemC reference kernel. Studied AT model achieved 13–40x speedup with modest 10% estimation error.

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NORCHIP 2010

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