{"title":"超大规模集成电路中电感对互连传输延迟的影响","authors":"A. Ligocka, W. Bandurski","doi":"10.1109/SPI.2004.1409024","DOIUrl":null,"url":null,"abstract":"In the paper the analytical formula for the propagation delay of CMOS gate driving a distributed RLC line was derived. It is shown that obtained formula is more accurate in some cases than used in literature. The main idea of the presented approach is based on the expansion of the voltage unit step response into Taylor series. The coefficients of this expansion are calculated in symbolical manner in frequency domain as the moments determined for infinite frequency.","PeriodicalId":119776,"journal":{"name":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2004-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"Effect of inductance on interconnect propagation delay in VLSI circuits\",\"authors\":\"A. Ligocka, W. Bandurski\",\"doi\":\"10.1109/SPI.2004.1409024\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In the paper the analytical formula for the propagation delay of CMOS gate driving a distributed RLC line was derived. It is shown that obtained formula is more accurate in some cases than used in literature. The main idea of the presented approach is based on the expansion of the voltage unit step response into Taylor series. The coefficients of this expansion are calculated in symbolical manner in frequency domain as the moments determined for infinite frequency.\",\"PeriodicalId\":119776,\"journal\":{\"name\":\"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-05-09\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPI.2004.1409024\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 8th IEEE Workshop on Signal Propagation on Interconnects","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPI.2004.1409024","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Effect of inductance on interconnect propagation delay in VLSI circuits
In the paper the analytical formula for the propagation delay of CMOS gate driving a distributed RLC line was derived. It is shown that obtained formula is more accurate in some cases than used in literature. The main idea of the presented approach is based on the expansion of the voltage unit step response into Taylor series. The coefficients of this expansion are calculated in symbolical manner in frequency domain as the moments determined for infinite frequency.
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