MPEG-2传输流复用器的实现

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461) Pub Date : 1999-10-20 DOI:10.1109/SIPS.1999.822343

S.J. Kim, Jong-Seog Koh

{"title":"MPEG-2传输流复用器的实现","authors":"S.J. Kim, Jong-Seog Koh","doi":"10.1109/SIPS.1999.822343","DOIUrl":null,"url":null,"abstract":"In this paper we presents an ASIC implementation of MPEG-2 system transport stream (TS) multiplexer in compliance with ISO/IEC 13818-1. With built-in Peripheral Component Interconnect (PCI) I/O interface, the MPEG-2 system multiplexer chip can multiplex two programs: each program consists of a video, an audio and an additional host data as well as host selected Program Specific Information (PSI). Also host can control video and audio encoders which are developed through the PCI I/O interface. Our chipset supports compressed MP@ML video bit stream up to 15 Mbps and MPEG-2 audio bit stream up to 1.2 Mbps. It is applicable to HDTV multiplexer. It has been described by VHDL. Its gate-level optimization and simulation has been performed using COMPASS CAD tool. Our implementation result shows about 81000 equivalent gate counts with 50000 bits of memory. Some specific features of our chipset will be presented in the paper.","PeriodicalId":275030,"journal":{"name":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","volume":"94 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"An implementation of MPEG-2 transport stream multiplexer\",\"authors\":\"S.J. Kim, Jong-Seog Koh\",\"doi\":\"10.1109/SIPS.1999.822343\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we presents an ASIC implementation of MPEG-2 system transport stream (TS) multiplexer in compliance with ISO/IEC 13818-1. With built-in Peripheral Component Interconnect (PCI) I/O interface, the MPEG-2 system multiplexer chip can multiplex two programs: each program consists of a video, an audio and an additional host data as well as host selected Program Specific Information (PSI). Also host can control video and audio encoders which are developed through the PCI I/O interface. Our chipset supports compressed MP@ML video bit stream up to 15 Mbps and MPEG-2 audio bit stream up to 1.2 Mbps. It is applicable to HDTV multiplexer. It has been described by VHDL. Its gate-level optimization and simulation has been performed using COMPASS CAD tool. Our implementation result shows about 81000 equivalent gate counts with 50000 bits of memory. Some specific features of our chipset will be presented in the paper.\",\"PeriodicalId\":275030,\"journal\":{\"name\":\"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)\",\"volume\":\"94 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1999-10-20\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SIPS.1999.822343\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SIPS.1999.822343","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 6

摘要

本文提出了一种符合ISO/ iec13818 -1标准的MPEG-2系统传输流(TS)多路复用器的ASIC实现。内置外围组件互连(PCI) I/O接口，MPEG-2系统多路复用芯片可以复用两个程序:每个程序由视频，音频和额外的主机数据以及主机选择的程序特定信息(PSI)组成。主机还可以控制通过PCI I/O接口开发的视频和音频编码器。我们的芯片组支持压缩MP@ML视频比特流高达15 Mbps和MPEG-2音频比特流高达1.2 Mbps。适用于HDTV多路复用器。用VHDL对其进行了描述。利用COMPASS CAD工具对其进行了门级优化和仿真。我们的实现结果显示大约81000等效门计数与50000位内存。本文将介绍我们芯片组的一些具体功能。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文本刊更多论文

An implementation of MPEG-2 transport stream multiplexer

In this paper we presents an ASIC implementation of MPEG-2 system transport stream (TS) multiplexer in compliance with ISO/IEC 13818-1. With built-in Peripheral Component Interconnect (PCI) I/O interface, the MPEG-2 system multiplexer chip can multiplex two programs: each program consists of a video, an audio and an additional host data as well as host selected Program Specific Information (PSI). Also host can control video and audio encoders which are developed through the PCI I/O interface. Our chipset supports compressed MP@ML video bit stream up to 15 Mbps and MPEG-2 audio bit stream up to 1.2 Mbps. It is applicable to HDTV multiplexer. It has been described by VHDL. Its gate-level optimization and simulation has been performed using COMPASS CAD tool. Our implementation result shows about 81000 equivalent gate counts with 50000 bits of memory. Some specific features of our chipset will be presented in the paper.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

1999 IEEE Workshop on Signal Processing Systems. SiPS 99. Design and Implementation (Cat. No.99TH8461)

自引率

0.00%

发文量