A New VLSI Algorithm for an Efficient VLSI Implementation of Type IV DST based on Short Band- Correlation Structures

A new VLSI algorithm for a prime length DST IV transform that can be efficiently implemented in parallel using linear systolic arrays is presented. The proposed algorithm represent the key for an efficient VLSI implementation with a high throughput and can be efficiently mapped on linear systolic arrays with a small number of I/O channels and a low I/O bandwidth. The proposed algorithm uses an efficient computational structure called pseudo-band correlation structure. It can be implemented as efficient as other similar computation structures as cycle convolution and circular correlation. This leads to an efficient VLSI chip with appealing features from a VLSI implementation point of view as regularity, modularity and short interconnections. We can obtain similar performances as high processing speed, low hardware cost and low I/O costs similar with that obtained using cycle convolution and circular correlation.