在65nm CMOS中采用2D差分功率组合实现输出功率密度为74.5mW/mm2的53- 73ghz功率放大器

2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC) Pub Date : 2013-06-02 DOI:10.1109/RFIC.2013.6569580

Wei Fei, Hao Yu, W. M. Lim, Junyan Ren

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引用次数: 11

摘要

为实现60GHz功率放大器在65nm CMOS上的宽带宽和高输出功率密度设计，本文介绍了一种基于超材料的零移相器的二维差分功率组合网络。同时实现分布式放大和功率组合，提高了功率密度和带宽的性能。PA测量结果显示，在0.262 mm2的面积内，增益13.2 dB, PAE 8.7%， P1dB 13dBm，带宽20GHz (53 ~ 73GHz)。

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A 53-to-73GHz power amplifier with 74.5mW/mm2 output power density by 2D differential power combining in 65nm CMOS

Towards wide bandwidth and high output power density for 60GHz PA design in 65nm CMOS, this paper introduces a 2D differential power combining network by metamaterial-based zero-phase-shifter. Simultaneous distributed amplification and power combining can be achieved with improved performances in both power density and bandwidth. The PA measurement results show 13.2 dB gain, 8.7% PAE, 13dBm P1dB, and 20GHz bandwidth (53 to 73GHz) within an area of 0.268mm2.

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2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)

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