一种新型900 MHz I × V CMOS乘法器

J. Mateus, Alejandro Dias-Sanchez
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引用次数: 0

摘要

本文提出了一种带FVFCS的电流电压乘法器。该倍增器利用FVFCS的极低阻抗输入节点来感知电流信号。另外,使用两个交叉耦合的差分对,以消除输出电流中不需要的分量。采用标准的混合和RF 180nm UMC CMOS工艺进行了仿真,并与先前报道的乘法器进行了比较。该倍增器的带宽为900 MHz,静态电流为203 μ a。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
A Novel 900 MHz I x V CMOS Multiplier
In this paper a currentxvoltage multiplier with the FVFCS is presented. This wultiplier takes advantage of the very low–impedance input node of the FVFCS to sense the current signals. Additionally, uses a two cross–coupled differential pairs in order to cancel undesired components in the output current. The simulations are carried out using the standard Mixed and RF 180 nm UMC CMOS process and is compared with a previous reported multiplier. The presented multiplier has a bandwidth of 900 MHz with a quiescent current of 203 ?A.
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