基于逻辑门的区域高效延迟PUF

Dongxing Wang, Leibo Liu, Bo Wang, Shaojun Wei
{"title":"基于逻辑门的区域高效延迟PUF","authors":"Dongxing Wang, Leibo Liu, Bo Wang, Shaojun Wei","doi":"10.1109/iccsn.2018.8488275","DOIUrl":null,"url":null,"abstract":"As a promising circuit primitive, Physical Unclonable Function (PUF) draws extensive attention and research. PUF can extract features of integrated circuits (ICs) from random process variations and be applied for identification, device authentication and secret key generation, etc. To improve the security of PUF, the outputs of independent PUFs are XOR-mixed together, which requires more circuits. In this paper, we propose an area-efficient delay-based PUF based on logic gates, which exploits delay differences of logic gates. To improve the security of the PUF, an output network is designed to combine the outputs from multiple delay lines. It has been demonstrated that the PUF satisfies the Strict Avalanche Criterion (SAC) and can pass NIST randomness test. SPICE-based evaluation using TSMC 65nm technology validates the high uniqueness of the PUF. Synthesized results with the Synopsys Design Compiler of PUFs using TSMC 65nm technology validate their low area overhead.","PeriodicalId":243383,"journal":{"name":"2018 10th International Conference on Communication Software and Networks (ICCSN)","volume":"51 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Area-Efficient Delay-based PUF Based on Logic Gates\",\"authors\":\"Dongxing Wang, Leibo Liu, Bo Wang, Shaojun Wei\",\"doi\":\"10.1109/iccsn.2018.8488275\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"As a promising circuit primitive, Physical Unclonable Function (PUF) draws extensive attention and research. PUF can extract features of integrated circuits (ICs) from random process variations and be applied for identification, device authentication and secret key generation, etc. To improve the security of PUF, the outputs of independent PUFs are XOR-mixed together, which requires more circuits. In this paper, we propose an area-efficient delay-based PUF based on logic gates, which exploits delay differences of logic gates. To improve the security of the PUF, an output network is designed to combine the outputs from multiple delay lines. It has been demonstrated that the PUF satisfies the Strict Avalanche Criterion (SAC) and can pass NIST randomness test. SPICE-based evaluation using TSMC 65nm technology validates the high uniqueness of the PUF. Synthesized results with the Synopsys Design Compiler of PUFs using TSMC 65nm technology validate their low area overhead.\",\"PeriodicalId\":243383,\"journal\":{\"name\":\"2018 10th International Conference on Communication Software and Networks (ICCSN)\",\"volume\":\"51 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 10th International Conference on Communication Software and Networks (ICCSN)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/iccsn.2018.8488275\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 10th International Conference on Communication Software and Networks (ICCSN)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/iccsn.2018.8488275","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0

摘要

物理不可克隆函数(Physical unclable Function, PUF)作为一种很有前途的电路原语,受到了广泛的关注和研究。PUF可以从随机工艺变化中提取集成电路的特征,并应用于身份识别、设备认证和密钥生成等方面。为了提高PUF的安全性,独立PUF的输出被xor混合在一起,这需要更多的电路。本文提出了一种基于逻辑门的延时PUF,利用了逻辑门的延时差异。为了提高PUF的安全性,设计了一个输出网络,将多个延迟线的输出组合在一起。结果表明,该PUF满足严格雪崩准则(SAC),并能通过NIST随机检验。采用台积电65nm技术的spice评估验证了PUF的高度独特性。采用台积电65nm技术的puf的Synopsys设计编译器合成结果验证了其低面积开销。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Area-Efficient Delay-based PUF Based on Logic Gates
As a promising circuit primitive, Physical Unclonable Function (PUF) draws extensive attention and research. PUF can extract features of integrated circuits (ICs) from random process variations and be applied for identification, device authentication and secret key generation, etc. To improve the security of PUF, the outputs of independent PUFs are XOR-mixed together, which requires more circuits. In this paper, we propose an area-efficient delay-based PUF based on logic gates, which exploits delay differences of logic gates. To improve the security of the PUF, an output network is designed to combine the outputs from multiple delay lines. It has been demonstrated that the PUF satisfies the Strict Avalanche Criterion (SAC) and can pass NIST randomness test. SPICE-based evaluation using TSMC 65nm technology validates the high uniqueness of the PUF. Synthesized results with the Synopsys Design Compiler of PUFs using TSMC 65nm technology validate their low area overhead.
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