Exploiting adder compressors for power-efficient 2-D approximate DCT realization

This paper proposes the use of efficient adder compressors for the power-efficient 2-D Discrete Cosine Transform (DCT) implementation. Due to the increasing use of the discrete transforms in image compression, and its dedicated hardware design, the search for efficient and fast approaches to the DCTs reached a special place in the state-of-art researches. The DCT is an approximation of the cosine function, whose resultant matrix is only composed of 0 and 1 values. Therefore, the DCT can be easily implemented using only adders and subtractors rather than general purpose multipliers. In this work we use combinations of efficient 4-2 and 8-2 adder compressors for the state-of-the approximate DCT implementations. The approximate DCT performance combined with its lower computational effort makes this transform an excellent choice to be applied to dedicated hardware for image compression. We present an environment for the synthesis of the DCTs in Cadence Encounter RTL Compiler tool. The synthesis reports are based on a set of true images as input vectors in order to obtain valid power results. The results show that the hardwired state-of-the-art approximate DCT solutions, with adder compressors, minimizes both cells area and power consumption with good overall quality images.