基于低功耗fpga的高斯混合背景减相法

2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines Pub Date : 2013-12-15 DOI:10.1109/FCCM.2014.76

H. Tabkhi, Majid Sabbagh, G. Schirner

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引用次数: 9

摘要

本文简要介绍了一种基于fpga的全高清帧分辨率MoG背景减法的实现方法。我们的HW手工制作MoG由77个流水线级组成，在Zynq-7000 SoC上实现，工作频率为148.5 MHz。其结果是非常高的效率，功耗低于500兆瓦，比嵌入式软件解决方案效率高600倍。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A Power-Efficient FPGA-Based Mixture-of-Gaussian (MoG) Background Subtraction for Full-HD Resolution

This short paper briefly describes an FPGA-based realization of MoG background subtraction operating at fullHD frame resolution. Our HW hand-crafted MoG consists of 77 pipeline stages operating at 148.5 MHz implemented on a Zynq-7000 SoC. The results very high efficiency with a power consumption of less than 500 mW which is 600X more efficient than an embedded software solution.

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2014 IEEE 22nd Annual International Symposium on Field-Programmable Custom Computing Machines

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