{"title":"一种具有34.9% PAE和35.1 dBm输出功率的v波段GaN功率放大器","authors":"Pouria Pazhouhesh, J. Kitchen","doi":"10.1109/WMCS52222.2021.9493300","DOIUrl":null,"url":null,"abstract":"This work presents a high efficiency, highest reported output power GaN-based power amplifier targeting the V-band frequency range from 65 to 71 GHz. Implemented in HRL’s 40 nm GaN T3 MMIC process and simulated in AWR, the presented power amplifier achieves a simulated peak power added efficiency (PAE) of 34.9% at 66 GHz. The PA is composed of three stages, and the output stage uses a 4:1 Wilkinson power combiner. The PA’s maximum linear power gain is 13.3 dB at 68 GHz for an input power of 13 dBm. The maximum output power at 1dB compression point is 35.1 dBm at 68 GHz, associated with an input power of 23 dBm. The chip size is 2.7×4.9mm2, thus demonstrating a high power density of 245 mW/mm2 in simulation.","PeriodicalId":401066,"journal":{"name":"2021 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS)","volume":"529 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A V-Band GaN Power Amplifier with 34.9% PAE and 35.1 dBm Output Power\",\"authors\":\"Pouria Pazhouhesh, J. Kitchen\",\"doi\":\"10.1109/WMCS52222.2021.9493300\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work presents a high efficiency, highest reported output power GaN-based power amplifier targeting the V-band frequency range from 65 to 71 GHz. Implemented in HRL’s 40 nm GaN T3 MMIC process and simulated in AWR, the presented power amplifier achieves a simulated peak power added efficiency (PAE) of 34.9% at 66 GHz. The PA is composed of three stages, and the output stage uses a 4:1 Wilkinson power combiner. The PA’s maximum linear power gain is 13.3 dB at 68 GHz for an input power of 13 dBm. The maximum output power at 1dB compression point is 35.1 dBm at 68 GHz, associated with an input power of 23 dBm. The chip size is 2.7×4.9mm2, thus demonstrating a high power density of 245 mW/mm2 in simulation.\",\"PeriodicalId\":401066,\"journal\":{\"name\":\"2021 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS)\",\"volume\":\"529 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-05-18\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2021 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/WMCS52222.2021.9493300\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2021 IEEE Texas Symposium on Wireless and Microwave Circuits and Systems (WMCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/WMCS52222.2021.9493300","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
这项工作提出了一种高效率,最高输出功率的基于氮化镓的功率放大器,目标频率范围为65至71 GHz的v波段。在HRL的40 nm GaN T3 MMIC工艺中实现,并在AWR中进行仿真,该功率放大器在66 GHz时的模拟峰值功率增加效率(PAE)为34.9%。PA由三级组成,输出级采用4:1 Wilkinson功率合成器。当输入功率为13 dBm时,该放大器在68 GHz时的最大线性功率增益为13.3 dB。在68 GHz时,1dB压缩点的最大输出功率为35.1 dBm,对应的输入功率为23 dBm。芯片尺寸为2.7×4.9mm2,因此在模拟中显示了245 mW/mm2的高功率密度。
A V-Band GaN Power Amplifier with 34.9% PAE and 35.1 dBm Output Power
This work presents a high efficiency, highest reported output power GaN-based power amplifier targeting the V-band frequency range from 65 to 71 GHz. Implemented in HRL’s 40 nm GaN T3 MMIC process and simulated in AWR, the presented power amplifier achieves a simulated peak power added efficiency (PAE) of 34.9% at 66 GHz. The PA is composed of three stages, and the output stage uses a 4:1 Wilkinson power combiner. The PA’s maximum linear power gain is 13.3 dB at 68 GHz for an input power of 13 dBm. The maximum output power at 1dB compression point is 35.1 dBm at 68 GHz, associated with an input power of 23 dBm. The chip size is 2.7×4.9mm2, thus demonstrating a high power density of 245 mW/mm2 in simulation.