Stop the World: A Lightweight Runtime Power-Capping Mechanism for FPGAs

Power-constrained computing is now becoming essential paradigm in both high performance computing and embedded systems. Power budget is dynamically assigned to each computing resource for improving energy efficiency and system throughput. Modern computer systems have accelerator devices, such as GPUs and FPGAs, for higher energy efficiency and performance. Therefore, power management mechanisms of such accelerator devices are required. In this paper, we present a lightweight mechanism of runtime power capping on FPGA systems. According to the amount of a given power budget, instead of the frequency scaling, the proposed mechanism controls the execution speed by throttling off-chip memory accesses from the computing logic, so that the power consumption is accordingly controlled. We evaluated the power controllability of the proposed mechanism by using an FPGA board with an embedded power meter. The result shows that the proposed approach has a high linea rity of power control. The result also indicates that the accuracy of the power control depends on throttling interval granularities, and the control accuracy is improved by utilizing a longer throttling interval. Additionally, we compared the power control accuracy with a design-time fixed frequency scaling approach. The result shows that the proposed approach achieves the same accuracy as the static approach, even though the proposed approach allows the runtime power control.