{"title":"PCB高速母线组件退化的现场检测","authors":"S. Odintsov","doi":"10.1109/AUTEST.2018.8532547","DOIUrl":null,"url":null,"abstract":"Every mission-critical system goes through extensive functionality and stress tests after being manufactured. But these tests alone do not guarantee correct system behavior in the field. A contemporary high-performance system board is a complex 3D object that may contain a few dozens of hidden layers, stacked micro-vias, high density interconnect, with all above not contributing to ease of test and reliability. Today, data transmission rates on the board may be reaching multi-gigabit ranges on a single channel. Even small changes in high-speed transmission line's impedance caused by system degradation may result in system performance issues and increased error rates due to small delays, intermittent faults and other sporadic stability issues observed in certain operation modes, at certain workloads or manifesting in a seemingly stochastic manner. Diagnosing the root cause of such faulty behavior (defects) in the field is extremely difficult. Differently from Intermittent Faults, Marginal Defects are permanent imperfections, which do not have a temporary or periodic effect. In a way, they are similar to parametric variations, pushing the system (or more specifically, the assembled board) very close or slightly beyond its specified operating margins. As a remedy, high-speed signals are normally fine-tuned or even calibrated to deliver pitch perfect timing even in case of now-ubiquitous DDR3 memories. As a negative side, the calibration mechanism may mask Marginal Defects out until the operating window shrinks to unbearable size and system starts to fail. Self-test and various built-in monitors are often used to monitor system health status, predict and prepare for possible failures. In this paper, we will present methodology aimed at overcoming described above challenges and successfully monitor high-speed data transmission interface health. The methodology is based on observation of signal sampling delays deviation and method described in the previous paper [1].","PeriodicalId":384058,"journal":{"name":"2018 IEEE AUTOTESTCON","volume":"64 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"In-Field Detection of Degradation on PCB Assembly High-Speed Buses\",\"authors\":\"S. Odintsov\",\"doi\":\"10.1109/AUTEST.2018.8532547\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Every mission-critical system goes through extensive functionality and stress tests after being manufactured. But these tests alone do not guarantee correct system behavior in the field. A contemporary high-performance system board is a complex 3D object that may contain a few dozens of hidden layers, stacked micro-vias, high density interconnect, with all above not contributing to ease of test and reliability. Today, data transmission rates on the board may be reaching multi-gigabit ranges on a single channel. Even small changes in high-speed transmission line's impedance caused by system degradation may result in system performance issues and increased error rates due to small delays, intermittent faults and other sporadic stability issues observed in certain operation modes, at certain workloads or manifesting in a seemingly stochastic manner. Diagnosing the root cause of such faulty behavior (defects) in the field is extremely difficult. Differently from Intermittent Faults, Marginal Defects are permanent imperfections, which do not have a temporary or periodic effect. In a way, they are similar to parametric variations, pushing the system (or more specifically, the assembled board) very close or slightly beyond its specified operating margins. As a remedy, high-speed signals are normally fine-tuned or even calibrated to deliver pitch perfect timing even in case of now-ubiquitous DDR3 memories. As a negative side, the calibration mechanism may mask Marginal Defects out until the operating window shrinks to unbearable size and system starts to fail. Self-test and various built-in monitors are often used to monitor system health status, predict and prepare for possible failures. In this paper, we will present methodology aimed at overcoming described above challenges and successfully monitor high-speed data transmission interface health. The methodology is based on observation of signal sampling delays deviation and method described in the previous paper [1].\",\"PeriodicalId\":384058,\"journal\":{\"name\":\"2018 IEEE AUTOTESTCON\",\"volume\":\"64 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE AUTOTESTCON\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/AUTEST.2018.8532547\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE AUTOTESTCON","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AUTEST.2018.8532547","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
In-Field Detection of Degradation on PCB Assembly High-Speed Buses
Every mission-critical system goes through extensive functionality and stress tests after being manufactured. But these tests alone do not guarantee correct system behavior in the field. A contemporary high-performance system board is a complex 3D object that may contain a few dozens of hidden layers, stacked micro-vias, high density interconnect, with all above not contributing to ease of test and reliability. Today, data transmission rates on the board may be reaching multi-gigabit ranges on a single channel. Even small changes in high-speed transmission line's impedance caused by system degradation may result in system performance issues and increased error rates due to small delays, intermittent faults and other sporadic stability issues observed in certain operation modes, at certain workloads or manifesting in a seemingly stochastic manner. Diagnosing the root cause of such faulty behavior (defects) in the field is extremely difficult. Differently from Intermittent Faults, Marginal Defects are permanent imperfections, which do not have a temporary or periodic effect. In a way, they are similar to parametric variations, pushing the system (or more specifically, the assembled board) very close or slightly beyond its specified operating margins. As a remedy, high-speed signals are normally fine-tuned or even calibrated to deliver pitch perfect timing even in case of now-ubiquitous DDR3 memories. As a negative side, the calibration mechanism may mask Marginal Defects out until the operating window shrinks to unbearable size and system starts to fail. Self-test and various built-in monitors are often used to monitor system health status, predict and prepare for possible failures. In this paper, we will present methodology aimed at overcoming described above challenges and successfully monitor high-speed data transmission interface health. The methodology is based on observation of signal sampling delays deviation and method described in the previous paper [1].