BCD技术中p沟道LDMOS击穿电压的提高

C. Schmidt, G. Spitzlsperger
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引用次数: 3

摘要

提出了一种BCD技术的新概念,它包括对薄背面晶圆的处理,并提供-类似于SOI技术-电源器件的完全介电隔离。在传统的BCD技术中,p-LDMOS击穿电压的限制是通过在晶圆背面形成一个n+区域来取代通常应用的深n井层,并通过将n+区域与TSV连接到正面的源电位来克服的。制备的漂移长度为5.7μm的p-LDMOS击穿电压(BVdss)为- 115 V,导通电阻(Ron)为320 mΩ mm。通过TCAD仿真发现,通过在STI下方添加n型RESURF层,可以进一步优化p-LDMOS的BVdss、Ron和电SOA。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Increasing breakdown voltage of p-channel LDMOS in BCD technology with novel backside process
A novel concept for a BCD technology is presented which comprises the processing of the wafer on the thinned backside and which offers — similar to SOI technology — a full dielectric isolation of power devices. Limitations of the breakdown voltage of p-LDMOS encountered in conventional BCD technologies are overcome by replacing the commonly applied deep n well layer by an n+ region formed on the wafer backside and by connecting the n+ region with a TSV to the source potential on the front side. The fabricated p-LDMOS with drift length 5.7μm has a breakdown voltage (BVdss) of −115 V and an on-resistance (Ron) of 320 mΩ mm. It is found by TCAD simulations that further optimization of the p-LDMOS with respect to BVdss, Ron and electrical SOA can be achieved by adding an n-type RESURF layer below STI.
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