System-level model of a two-step locking technique applied in an all-digital Phase-locked loop

This paper proposes a system-level model of a new two-step locking technique for an all-digital phase-locked loop (ADPLL). The proposed design provides solutions for the trade-offs between the frequency resolution and locking range as well as between design complexity, area, and power consumption of the ADPLL system. As example, a system with reference frequency of 125 MHz and a locking frequency range from 5.375 GHz to 6.25 GHz is designed. The simulated phase-noise performance is -95 dBc/Hz at 1.25 MHz offset employing a division factor between 43 and 50.