V. Vidya, N. Zamdmer, T. Mechler, K. Onishi, D. Chidambarrao, B. Jeong, Y. Ko, C. H. Lee, J. Sim, M. Angyal, E. Crabbé
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Design and Analysis of Discrete FET Monitors in 7nm FinFET Product for Robust Technology Validation
This paper presents two phenomena captured by product-like analog layout design of experiments (DOEs) that are otherwise difficult to capture in foundry baseline test structures. Such product driven test structures are critical for early detection of yield detractors and robustly validating a technology in a fabless design environment.