Weiyan Zhang, Mehran Goli, Alireza Mahzoon, R. Drechsler
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引用次数: 1
摘要
在物联网(IoT)或其他网络物理系统(CPS)等许多应用中,对优化和高效嵌入式软件的需求正在增加。因此,嵌入式软件的早期性能分析对于执行设计空间探索(Design Space Exploration, DSE)、确保效率和满足上市时间限制是必不可少的。设计人员通常使用真实的硬件、模拟器或静态分析器来获得性能。然而,这些方法存在严重的缺陷,因为在设计过程的早期阶段无法获得真正的硬件,模拟器要么不支持任何计时精度,要么需要大量的执行时间,静态分析器需要硬件微架构的细节。在本文中,我们提出了一种新的基于人工神经网络(ANN)的方法,可以在RISC-V处理器的早期设计阶段快速准确地评估嵌入式软件的性能。这可以显著减轻设计人员执行DSE的负担。所提出的方法利用了动态分析技术和分析模型,并且不需要任何与微体系结构相关的参数,例如缓存未命中、缓存命中和内存级并行性。我们在速度和准确性方面比较了我们提出的独立于微架构的方法与最先进的方法。我们在各种基准测试上的实验表明,与电子系统级(ESL)的RISC-V虚拟样机(VP)相比,所提出的方法实现了4.41倍的加速,而估计结果的平均绝对百分比误差(MAPE)仅为2%。
ANN-based Performance Estimation of Embedded Software for RISC-V Processors
The demand for optimized and efficient embedded software is increasing in many applications such as the Internet of Things (IoT) or other Cyber-Physical Systems (CPS). Hence, early performance analysis of embedded software is essential to perform Design Space Exploration (DSE), ensure efficiency, and meet time-to-market constraints. Designers usually use real hardware, simulators, or static analyzers to obtain the performance. However, these methods suffer from serious drawbacks as real hardware is not available in the early stage of the design process, simulators either do not support any timing accuracy or require large execution time, and static analyzers need details of the hardware microarchitecture. In this paper, we present a novel Artificial Neural Network (ANN)-based approach that allows a fast and accurate performance estimation of embedded software for RISC-V processors in the early design phases. This can significantly reduce the burden on designers to perform DSE. The proposed approach takes advantage of the dynamic analysis technique and analytical models and does not require any microarchitecture-related parameters such as cache misses, cache hits, and memory-level parallelism. We compare our proposed microarchitecture-independent approach with state-of-the-art in terms of speed and accuracy. Our experiments on various benchmarks demonstrate that the proposed approach achieves a speed-up of $4.41\times$ compared to a RISC-V Virtual Prototype (VP) at the Electronic System Level (ESL), while the estimation results have only a Mean Absolute Percentage Error (MAPE) of 2%.