改进的Delta Sigma模数转换器

2011 International Conference on Computational Intelligence and Communication Networks Pub Date : 2011-10-07 DOI:10.1109/CICN.2011.93

A. Katara, S. Ramteke, A. Bapat, Swapnil Jain

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引用次数: 2

摘要

本文介绍了一种模数转换器，它将多个δ - σ调制器并联在一起，可以减少甚至消除过采样时间。通过将L阶δ - σ调制器的数量增加一倍，该结构的分辨率增加了大约L位。因此，通过将M个delta-sigma调制器并联而不进行过采样所获得的分辨率与以M的过采样率操作相同的调制器相似。本文描述了由两个、四个和八个二阶delta-sigma调制器组成的不需要过采样的并行delta-sigma A/D转换器实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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Improved Delta Sigma Analog to Digital Converter

This paper describes an analog-to-digital converter which combines multiple delta-sigma modulators in parallel so that time over sampling may be reduced or even eliminated. By doubling the number of Lth-order delta-sigma modulators, the resolution of this architecture is increased by approximately L bits. Thus, the resolution obtained by combining M delta- sigma modulators in parallel with no over sampling is similar to operating the same modulator with an over sampling rate of M. A parallel delta-sigma A/D converter implementation composed of two, four, and eight second-order delta-sigma modulators is described that does not require over sampling.

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2011 International Conference on Computational Intelligence and Communication Networks

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