On formulating and tackling integrated circuit placement as a scheduling problem

Integrated circuit (IC) placement consists of placing the cells of the IC on a chip plane so that overall performance is optimized. Various performance criteria have been considered with the most common being wire length. In this paper we tackle the problem with the optimization goal of reducing end to end delay, also called critical or longest path. We investigate the case where the chip plane has a priori (before placement) "sweet" spots, discuss its complexity and show the problem's relevance to job scheduling. In the experimental evaluation we provide hindsight on the optimization margins of scheduling heuristics.