Research on a high-precision SAR ADC based on non-binary redundancy structure

SAR ADC has the characteristics of simple structure, low power consumption, high energy efficiency and good process compatibility. Nowadays, more and more scenarios have higher requirements for the accuracy of SAR ADC. A 14bits SAR ADC with calibration function was designed based on a 0.18μm CMOS process. Design a DAC with a segmented non-binary redundant architecture. Segmented DACs effectively reduce area overhead, while non-binary weighting reduces the effect of capacitor mismatched accuracy, thereby improving ADC accuracy. The simulation condition is that the sampling rate is 1MSPS, and the simulation results show that: Using this calibrated SAR structure, the ENOB is 13.34bits, the SNR is 74.03dB, the SFDR is 81.36dB, and the THD is -79.20dB.