7|2个计数器和带有阈值逻辑的乘法

S. Vassiliadis, S. Cotofana
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引用次数: 7

摘要

我们提出了新的基于7|2计数器的阈值逻辑。特别地,我们展示了7|2计数器可以用三层门的阈值逻辑门实现,输出显式计算。因此,我们通过证明7|2计数器可以设计为两级门和隐式求和来改善延迟。我们进一步研究了使用这种计数器的乘法方案,结合Kautz(1961)的对称布尔函数网络。使用基于7|2隐式输出计算计数器和Kautz网络的32/spl times/32直接乘法方案,我们表明我们的方案在使用阈值逻辑的乘法的面积要求方面优于已知建议。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
7|2 counters and multiplication with threshold logic
We propose new threshold logic based, 7|2 counters. In particular we show that 7|2 counters can be implemented with threshold logic gates in three levels of gates with explicit computation of the outputs. Consequently, we improve the delay by showing that 7|2 counters can be designed with two levels of gates and implicit computation of the sum. Further we investigate multiplication schemes using such counters, in combination with Kautz's (1961) networks for symmetric Boolean functions. Using a 32/spl times/32 direct multiplication scheme based on 7|2 implicit output computation counters and the Kautz's networks we show that our scheme outperforms in terms of area requirements known proposals for multiplications using threshold logic.
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