{"title":"在标准CMOS制程中，STI相容高压NMOS与PMOS元件的设计与表征","authors":"Xiaolian Han, Chihao Xu","doi":"10.1109/ESSDERC.2007.4430907","DOIUrl":null,"url":null,"abstract":"This paper presents the design of High-Voltage NMOS and PMOS devices with STI (shallow trench isolation) technology fully compatible with a standard 0.25 mum/5 V CMOS process technology. Breakdown voltages of 35 V for n-channel with a specific on resistance of 1.96 mOmega.cm2 and -45 V for p-channel with a specific on-resistance of 8.73 mOmega.cm2 have been achieved without any modification of existing standard CMOS process.","PeriodicalId":103959,"journal":{"name":"ESSDERC 2007 - 37th European Solid State Device Research Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":"{\"title\":\"Design and characterization of STI compatible high-voltage NMOS and PMOS devices in standard CMOS process\",\"authors\":\"Xiaolian Han, Chihao Xu\",\"doi\":\"10.1109/ESSDERC.2007.4430907\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents the design of High-Voltage NMOS and PMOS devices with STI (shallow trench isolation) technology fully compatible with a standard 0.25 mum/5 V CMOS process technology. Breakdown voltages of 35 V for n-channel with a specific on resistance of 1.96 mOmega.cm2 and -45 V for p-channel with a specific on-resistance of 8.73 mOmega.cm2 have been achieved without any modification of existing standard CMOS process.\",\"PeriodicalId\":103959,\"journal\":{\"name\":\"ESSDERC 2007 - 37th European Solid State Device Research Conference\",\"volume\":\"20 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"3\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ESSDERC 2007 - 37th European Solid State Device Research Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ESSDERC.2007.4430907\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ESSDERC 2007 - 37th European Solid State Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ESSDERC.2007.4430907","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
摘要
本文介绍了采用STI(浅沟槽隔离)技术的高压NMOS和PMOS器件的设计，该技术完全兼容标准的0.25 μ m/5 V CMOS工艺技术。n通道击穿电压为35v，比电阻为1.96兆欧。cm2和-45 V的p通道，比导通电阻为8.73兆欧。在没有对现有标准CMOS工艺进行任何修改的情况下实现了cm2。
Design and characterization of STI compatible high-voltage NMOS and PMOS devices in standard CMOS process
This paper presents the design of High-Voltage NMOS and PMOS devices with STI (shallow trench isolation) technology fully compatible with a standard 0.25 mum/5 V CMOS process technology. Breakdown voltages of 35 V for n-channel with a specific on resistance of 1.96 mOmega.cm2 and -45 V for p-channel with a specific on-resistance of 8.73 mOmega.cm2 have been achieved without any modification of existing standard CMOS process.
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